1. Field of the Invention
The present invention relates to a data processing system, and more specifically to an address translation system for a microprocessor.
2. Description of Related Art
Conventional systems for translating an virtual address into a real address have been based on a construction method in which an address space is divided into a plurality of section spaces, each of which is divided into a plurality of area spaces, each of which is divided into a plurality of page spaces. In this case, a virtual address includes a virtual section number, a virtual area number, a virtual page number and a displacement or an offset within a page.
For example, an address translation system for translating the above mentioned virtual address into a real address comprises a group of area table registers one of which is selected on the basis of a virtual section number included in a given virtual address, area tables one of which is designated by the selected area table register and receives a virtual area number included in the given virtual address for designating an area space, and page tables one of which is designated by an output of the designated area table and receives a virtual page number included in the given virtual address for designating a page space.
In the above mentioned address translation system, accordingly, one area table register is selected from the group of area table registers in accordance with a virtual section number included a given virtual address. Then, an entry of an area table is designated by using a value stored in the selected area table register as a base address for an area table to be selected, and by using as an index a virtual area number included in the given virtual address. Furthermore, an entry of a page table is designated by using information outputted from the selected area table as a base address of a page table to be selected, and by using as an index a virtual page number included in the given virtual address. Thus, information outputted from the selected page table is a base address of a page frame within a main memory, and therefore, is combined with a displacement included in the given virtual address so as to obtain a real address.
Accordingly, the above mentioned address translation system comprises one set of registers and two kinds of address translation tables, and therefore, requires a substantial time for address translation. If all address translations are performed in this method, performance greatly falls down.
In view of this disadvantage, the conventional address translation system has been associated with an address translation retrieval buffer or translation look-aside buffer (TLB) so as to shorten the time required for the address translation. This translation look-aside buffer is composed of an associative memory, and stores a plurality of entry-address sets, an entry of each set being composed of one combination of a virtual section number, a virtual area number and a virtual page number, and an address of each set being composed of, for example, a page frame address within a main memory corresponding to the combination of the virtual section number, the virtual area number and the virtual page number defined in the associated entry.
In the case that the translation look-aside buffer is provided, when an virtual address is given, the translation look-aside buffer is retrieved in order to find an entry which is the same as the given virtual address all in the virtual section number, in the virtual area number and in the virtual page number. If an entry completely coincident with these virtual numbers is found, a corresponding real page number can be immediately obtained, and therefore, the obtained real page number is combined with a displacement included in the given virtual address, so that a real address is easily obtained. However, if an entry coincident with the virtual numbers is not found, namely, if the translation look-aside buffer does not hit, two stages of table retrieval must be retrieved.